When I attempt to generate an IBERT core for my Virtex-6 device, implementation fails with the following messages in the console:
BERT:par on chipscope_ibert
ERROR:sim - Error: Par failed. Timing for this design was not met. Reduce the number of GTs enabled, reduce your line rate, and/or choose a faster device.
Error found during generation.
How do I work around this issue?
The issue in PAR failure is a timing error that appears when a GT's TXOUTCLK is used to generate a system clock in IBERT.
A work-around is to use a dedicated input clock as System Clock instead of a GTs TXOUTCLK. For ML623 and ML605 boards, this includes the 200 MHz LVDS system clock that comes in on the J9 pin.
If you need to use TXOUTCLK as your system clock, please open an online WebCase with Xilinx Customer Support: