Description

When I try to generate a core for Virtex-6 or Spartan-6 families using ISE 11.3 I receive the following error message :

ERROR:coreutil - XST has returned an error: ERROR:HDLCompiler:432 

Solution

During synthesis, XST now checks that the generated core meets the IEEE VHDL Standard and is LRM (Language Reference Manual) compliant. 

As a result of these checks, since ISE 11.3 the core will not generate for Virtex-6 or Spartan-6 families. 

A patch for this issue has been created. See (Xilinx Answer 33617) for more information and to obtain the patch. 

It will still generate a netlist for older families. 

Please see (Xilinx Answer 30631 ) for a detailed list of LogiCORE 3GPP LTE Turbo Encoder Release Notes and Known Issues.

Linked Answer Records

Associated Answer Records