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AR# 33644

Design Advisory for Xilinx Solutions for Forward Error Correction Cores including Virtex-6, Spartan-6, and Virtex-5 FPGA

Description

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

Solution

For a list of all current Release Notes and Known Issues for Xilinx Solutions for Digital Communication Cores, please refer to the IP Release Notes Guide:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Virtex-6 and Spartan-6 solution for LTE 3GPP Turbo Encoder v3.0

(Xilinx Answer 33617) LogiCORE 3GPP LTE Turbo Encoder v3.0 - Release Notes/README for 3GPP LTE Turbo Encoder v3.0 rev 1 Patch

To update your Xilinx Alert Notification Preferences, please update your MyProfile page:

https://secure.xilinx.com/webreg/register.do?group=myprofile

Revision History

10/13/2009 - Initial Release; Added 33617

AR# 33644
Date Created 10/13/2009
Last Updated 12/15/2012
Status Active
Type General Article