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AR# 33657

11.3 Timing/Virtex5 - Clock Skew analysis appears to large for the clock topology


When I run timing analysis on my design, the clock skew appears to large for the simple clock topology.

This clock skew is from cross clock domain analysis. ClockA is a DCM -> BUFG -> PLL -> BUFG and ClockB is a DCM -> BUFG -> PLL -> BUFG.

When is this going to be fixed?


This issue is scheduled to be fixed in the next major release of the software, which is 11.4.

AR# 33657
Date 12/15/2012
Status Active
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
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  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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