It is required that the C_BASEADDR must start on an integer multiple of 512K (0x0000_0000, 0x0008_0000, 0x0018_0000, etc).
The design file, addr_response_shim.vhd, was incorrectly using the PLB address bits 12-31 to decode the address when it should have been using bits PLB address bits 13-31. As a result, C_BASEADDR=0x00080000 and C_HIGHADDR=0x000FFFFF fail in hardware.
1. Download the archive:
2. Extract the ZIP file to a temporary folder.
3. Copy the xps_ll_temac_v2_02_a pcore from the installed EDK pcore directory, $XILINX_EDK\hw\XilinxProcessorIPLib\pcores\) to the local pcore directory.
4. Replace the xps_ll_temac_v2_02_a\hdl\vhdl\addr_response_shim.vhd file with the file in the archive.
5. Rescan the user repository and reimplement the design.
The first release with this fix is EDK 11.4.