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AR# 33699

Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Polarity Reversal on Lane 7 Could Cause the Core Not to Train all 8 Lanes

Description

Known Issue: v1.12, v1.11, v1.10.1, v1.10, v1.9.4, v1.9.3, v1.9.2, v1.9.1, v1.9, v1.8, v1.7.1, v1.6., v1.5, v1.4, v1.3, v1.2, v1.1

Polarity reversal on lane 7 (numbering from 0) might cause the Block Plus core not to train as an x8, but instead train as an x4.

Solution


This problem occurs due to a mistake in the prod_fixes.v Block Plus wrapper source code file. This issue causes the block to not be able to detect the polarity reversal on lane 7 and assert the gt_rx_polarity input to the lane 7 MGT to reverse the data. This causes the link to fail to train as a x8, and then train to the next available link width or x4.

In v1.12 and later, the wrapper source files are now delivered with the generated core. To fix this issue, place the "prod_fixes.v" file (found in the zip file below) in the directory <generated_core_name>/source.

If you are using the v1.11 core, you will need to place the file into the following folder:
C:\Xilinx\11.1\ISE\coregen\ip\xilinx\network\com\xilinx\ip\pcie_blk_plus_v1_11\pcie_top\

Or, a similar path for your installation.

Regenerate the v1.11 core from the CORE Generator software.

The zip containing the workaround is found at:
http://www.xilinx.com/txpatches/pub/applications/pci/ar33278_bp_v1_12_files.zip

Note that this zip file contains workarounds for other issues in v1.12. Please see the "readme.txt" in the zip file for more information.

This workaround file should not be used on cores prior to v1.11.

These fixes are scheduled to be included in the v1.13 Block Plus Core (included in ISE Design Suite 11.4).

Revision History
07/05/2011 - Updated title
10/26/2009 - Initial Release
AR# 33699
Date Created 10/23/2009
Last Updated 07/05/2011
Status Active
Type ??????
IP
  • Endpoint Block Plus Wrapper for PCI Express