12.1/11.x ChipScope Pro - IBERT generation fails on a Virtex-6 device when I enable 8 or more GTs

AR#	33701	Search For Another Answer
Topic	ChipScope
Last Updated	09/21/2010
Status	Active

Description

When I enable 8 or more GTs in my IBERT design, I see implementation errors in MAP or XST:

"ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>" has been changed to Internal"

"ERROR:Place:1145 - Unroutable Placement! A GT / BUFGCTRL clock component"

"ERROR:Pack:2310 - Too many comps of type "BUFG" found to fit this device."

"ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as "

Solution

To work around this issue, enable less GTs in the IBERT core. This might mean that you cannot test all GTs with one core.

This issue is scheduled to be resolved in a future release of ChipScope Pro IBERT 12.4If you require further assistance and need to test a larger number of GTs, open a WebCase with Xilinx Customer Support at:
http://www.xilinx.com/support/clearexpress/websupport.htm