AR #33701 - 11.3 ChipScope IBERT - "ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>"
11.3 ChipScope IBERT - "ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>"
| AR# | 33701 |
| Part | SW-ChipScope IBERT |
| Last Modified | 2009-10-21 00:00:00.0 |
| Status | Active |
| Keywords | GTP, GTX, JTAG, bit, error, transceiver, characterize, GT, RX, TX |
Description
Keywords: GTP, GTX, JTAG, bit, error, transceiver, characterize, GT, RX, TX
When I enable 12 or more GTs in my IBERT design, the following error occurs:
"ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>"
How do I work around this issue?
Solution
To work around this issue, enable less GTs in the IBERT core.This issue is scheduled to be resolved in a future release of ChipScope Pro IBERT. If you require further assistance, open a WebCase with Xilinx Customer Support at:
http://www.xilinx.com/support/clearexpress/websupport.htm