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AR# 33701

12.1/11.x ChipScope Pro - IBERT generation fails on a Virtex-6 device when I enable 8 or more GTs


When I enable 8 or more GTs in my IBERT design, I see implementation errors in MAP or XST:

"ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>" has been changed to Internal"

"ERROR:Place:1145 - Unroutable Placement! A GT / BUFGCTRL clock component"

"ERROR:Pack:2310 - Too many comps of type "BUFG" found to fit this device."

"ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as "


To work around this issue, enable less GTs in the IBERT core. This might mean that you cannot test all GTs with one core.

This issue is scheduled to be resolved in a future release of ChipScope Pro IBERT 12.4If you require further assistance and need to test a larger number of GTs, open a WebCase with Xilinx Customer Support at:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35269 12.x ChipScope Pro - Known Issues for the ChipScope Pro 12.x software N/A N/A
AR# 33701
Date Created 10/21/2009
Last Updated 01/02/2013
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ChipScope Pro - 11.3
  • ChipScope Pro - 11.4
  • ChipScope Pro - 11.5
  • More
  • ChipScope Pro - 11.1
  • ChipScope Pro - 11.2
  • ChipScope Pro - 12.1
  • Less