Spartan-6 FPGA - LX75 and LX75T I/O Connectivity Issue in ISE Design Suite 11.3
Description
Keywords: Design Advisory, CSG484, FGG676, 75, 75T, 11.4
An issue was found with the Spartan-6 FPGA LX75 and LX75T device models in ISE Design Suite 11.3. The issue affects the locations of the I/O pads relative to the fabric and is scheduled to be fixed in the ISE Design Suite 11.4 release.
Solution
Any designs targeting the Spartan-6 FPGA LX75 or LX75T in 11.3 will need to be re-implemented in ISE Design Suite 11.4. The changes to the pad locations will change the design timing and could invalidate some routing. Although the package file and documentation are correct, some pin locations used in ISE Design Suite 11.3 might not be possible or efficient when the design is re-routed for the updated device model in 11.4. Customers should not lock down pin-outs or commit to boards for the LX75 or LX75T until they have implemented their design using ISE Design Suite 11.4.Only one package was made available for each of these devices in ISE Design Suite 11.3; the CSG484 package for the LX75 device, and the FGG676 package for the LX75T device. No other packages or device densities are affected. No pin-outs in ISE Design Suite 11.3 have changed, and all Spartan-6 FPGA part/package combinations will be supported in ISE Design Suite 11.4.
Contact Xilinx Technical Support if you have questions on this issue, or for addition information:
http://www.xilinx.com/support/