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AR# 33706

MIG v3.3 - Release Notes and Known Issues for ISE Design Suite 11.4

Description

This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.3 released in ISE Design Suite 11.4 and contains the following information:

  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

MIG v3.3 is available through ISE Design Suite 11.4.

For a list of supported memory interfaces and frequencies for Spartan-3 Generation, Virtex-4, and Virtex-5 FPGA, see the MIG User Guide:
http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide:
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf

For a list of supported Spartan-6 FPGAs, see (Xilinx Answer 33234).

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide:
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

Software Requirements

  • Xilinx ISE Design Suite 11.4
  • Synplify Pro C-2009.06-sp1 support
  • 32-bit Windows XP
  • 32-bit Linux Red Hat Enterprise 4.0
  • 64-bit/32-bit Linux Red Hat Enterprise 4.0
  • 64-bit XP professional
  • 32-bit Vista business
  • 64-bit SUSE 10
  • 64-bit/32-bit Linux Red Hat Enterprise 5.0 support
  • 64-bit Windows Vista support
  • 32-bit SUSE 10 support

New Features

  • ISE Design Suite 11.4 software support
  • VHDL support for all Virtex-6 FPGA designs
  • Synplify Pro C-2009.06-sp1 support for Virtex-6 FPGA QDRII+ and RLDRAM Designs
  • Support for Xilinx Reference Board information for Virtex-6 and Spartan-6 devices
  • Outer banks support for Virtex-6 RLDRAM II designs
  • Outer banks support for Address/Control and Data Write for Virtex-6 FPGA QDRII+ designs
  • Support of 1.5v or 1.8v I/O Voltage selection for Virtex-6 RLDRAM II designs
  • System Control group is allocated in System Clock bank and removed the System Control group selection forVirtex-6 FPGA designs in GUI bank selection page
  • Support for Spartan-6 -1L devices
  • Support for Differential or Single ended System Clock selection for Spartan-6 FPGA in MIG GUI
  • Support for Pin/Bank selection feature for Virtex-5 FPGA DDR2 SDRAM, DDR SDRAM, and QDRII SRAM designs
  • CDC file support for all debug enabled designs and Xilinx reference boards
  • Virtex-5 FPGA multi-controller designs support different frequencies for different interfaces
  • Frequency selection changed to clock period in MIG GUI for all designs of all FPGA families

Resolved Issues

DDR2/DDR3 SDRAM Virtex-6 FPGA

  • (Xilinx Answer 33288) MIG v3.2, Virtex-6 FPGA DDR2/3 - Calibration does not complete or completes incorrectly for x4 memory parts
  • (Xilinx Answer 33389) MIG v3.2, Virtex-6 FPGA DDR3 - ODT values incorrectly set for component-based design
  • (Xilinx Answer 33403) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - Simulation warnings are generated for mismatches in port connection sizes
  • (Xilinx Answer 33405) MIG v3.2 Virtex-6 FPGA DDR2/DDR3 - When data mask is disabled, BitGen will fail with PhysDesignRules errors
  • (Xilinx Answer 33409) MIG v3.2, Virtex-6 FPGA DDR2 and DDR3 - Traffic Generator (example_design) does not support DDR2 BL=4 and DDR2/DDR3 Data Widths greater then 72-bits
  • (Xilinx Answer 33415) MIG v3.2, Virtex-6 FPGA DDR2DDR3 - Master Bank selection is not enabled in some cases which require a Master Bank
  • (Xilinx Answer 33419) MIG v3.2, Virtex-6 FPGA DDR3: No support available for CWL=8 for RDIMM devices
  • (Xilinx Answer 33420) MIG v3.2, Virtex-6 FPGA DDR2 - No support for CL=6 with RDIMM devices
  • (Xilinx Answer 33439) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - ECC not supported for data widths equal to 120-bit
  • (Xilinx Answer 33440) MIG v3.2, Virtex-6 FPGA DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration
  • (Xilinx Answer 33442) MIG v3.2, Virtex-6 FPGA DDR3: tRP violations may occur in simulation because of a rounding error
  • (Xilinx Answer 33443) MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - Read associated with Read Modified Write command is incorrectly issued as a Read with Auto-Precharge
  • (Xilinx Answer 33613) MIG v3.2, Virtex-6 DDR2/DDR3 - Design incorrectly assigns app_wdf_mask (user interface data mask) to 0 preventing the ability to mask data

QDRII+ SRAM Virtex-6 FPGA

  • (Xilinx Answer 33378) MIG v3.2, Virtex-6 FPGA QDRII+/RLDRAMII - Half-cycle path from ISERDES to clk_RD is not required
  • (Xilinx Answer 33413) MIG v3.2, Virtex-6 FPGA QDRII+ SRAM - The output example_top.ucf is missing the system clock period constraint and includes an incorrect BUFR constraint

RLDRAMII Virtex-6 FPGA

  • (Xilinx Answer 33375) MIG v3.2, Virtex-6 FPGA RLDRAMII - Valid configurations to avoid tRC violations for -18, -25, -25E, and -33 devices
  • (Xilinx Answer 33376) MIG v3.2, Virtex-6 FPGA RLDRAMI - MAX tCK violations occur in simulation for -18 parts running at 370 MHz
  • (Xilinx Answer 33378) MIG v3.2, Virtex-6 FPGA QDRII+/RLDRAMII - Half-cycle path from ISERDES to clk_RD is not required
  • (Xilinx Answer 33402) MIG v3.2, Virtex-6 FPGA RLDRAMII - Data Mask signals are not properly propagated through the write path - RTL CHANGES REQUIRED
  • (Xilinx Answer 33446) MIG v3.2, Virtex-6 FPGA RLDRAMII - "ERROR:Bitgen - Could not find programming information" occurs for the XC6VLX760-FF1760 device

Spartan-6 FPGA MCB

  • (Xilinx Answer 33356) Spartan-6 FPGA MCB - X4 memory components are not supported until IDS 11.4 (MIG 3.3)
  • (Xilinx Answer 33357) Spartan-6 FPGA MCB - Port 3 is not supported in read mode when all 6 ports are configured
  • (Xilinx Answer 33608) MIG v3.2 - Spartan-6 FPGA MCB - ise_flow.bat is missing the -w switch in the MAP command
  • Example_Top address space assignment is corrected for configuring two 32-bit bi-directional ports and four 32-bit readports (i.e., B32B32R32R32R32R32)
  • CR 531540
  • CR 531539

DDR2 SDRAM Virtex-5 FPGA

  • Missing signal is added to the sensitivity list for Virtex-5 DDR2 SDRAM ddr2_phy_init.vhd module
  • CR 532395
  • Calibration algorithm made more robust to fix possible errors in stage3 calibration
  • CR 534675

DDR SDRAM Virtex-5 FPGA

QDRII SRAM Virtex-5 FPGA

  • CLK_PERIOD parameter is mapped to the qdrii_phy_dly_cal_sm instance in qdrii_phy_read.vhd module, this was missing in earlier versions
  • CR 533793

DDRII SRAM Virtex-5 FPGA

  • CLK_PERIOD parameter is mapped to the ddrii_phy_dly_cal_sm instance in ddii_phy_io.vhd module, this was missing inearlier versions
  • CR 533793

DDR2 SDRAM Virtex-4 FPGA Direct Clocking

DDR2 SDRAM Virtex-4 FPGA Serdes Clocking

DDR SDRAM Virtex-4 FPGA

QDRII SRAM Virtex-4 FPGA

DDRII SRAM Virtex-4 FPGA

DDR/DDR2 SDRAM Spartan-3 FPGA

  • Updates to Virtex-5, Virtex-4, and Spartan-3 Generation FPGA MIG User Guide (UG086)
  • Updated implementation guidelines section for QDRII Virtex-5 FPGA according to XAPP853
  • CR 537526
  • Added detailed description on Errors in Verify UCF/Update Design and UCF
  • CR 526296

MIG Tool

  • (Xilinx Answer 33414) MIG v3.2, Virtex-4/Virtex-5 FPGA DDR/DDR2 - MIG GUI incorrectly enables Data Mask check box for X4 RDIMM parts which do not have a DM
  • CR 535859
  • CR 534275
  • Added -w switch to ise_flow.bat file in the map command
  • CR 534872
  • Corrected OUTPUT_DRV parameter values for RZQ/6 it is "LOW" and for RZQ/7 it is "HIGH". Also changed"Output Drive Strength" to "Output Impedance Control" in MIG GUI.
  • CR 534500
  • For Virtex-5 XC5VLX20T-FF323 device, MIG restricts the multi controller selection either to DDR2 SDRAM or QDR2 SRAMinterface as this FPGA has only single PLL support
  • CR 533859
  • MIG disables the Data Mask signals for memory part DDR3 SDRAM RDIMM, MT18JSF25672PY-1G1, as this part does not support Data Mask bits
  • CR 533794
  • UCF period constraint reference is changed to input source pin name from internal net name for Virtex-6 DDR2/DDR3designs. It is possible to rename the internal net name by synthesis tools.
  • CR 533011
  • UCF clock constraints are generated for both the interfaces for multi interface designs. Clock constraint for thesecond interface was missing in 3.2 release.
  • CR 532920
  • MIG supports sim.do file for DDR2 SDRAM ELPIDA parts for Spartan-6 designs
  • CR 532113
  • Corrected the missing and incorrect UCF clock constraints for Virtex-6 QDRII+ designs
  • CR 531921
  • Changed the multi-cycle constraint in UCF from "TS_sys_clk"*8 to "TS_sys_clk"*4 for Virtex-6 DDR3 SDRAM designs,because Ts_sys_clk is half the memory frequency
  • CR 531913
  • Issues related to Master Bank enabling are fixed
  • CR 531846
  • Setting of PHASE_DETECT parameter is conditioned with frequency in sim_tb_top module for all Virtex-6 designs. Itwas always OFF in sim_tb_top module in 3.2 release because of MTI issues
  • CR 531798
  • Removed the half cycle path UCF constraints from ISERDES output to the falling edge of clk_rd for Virtex-6QDR2+ designs
  • CR 531754
  • Removed the half cycle path UCF constraints from ISERDES output to the falling edge of clk_rd for Virtex-6RLDRAM II designs
  • CR 531753
  • MIG outputs only the Micron memory models and for other models it provides links to exact location of the models
  • CR 531711
  • Included tb_top.v/vhd file to .prj files list that gets generated under sim folder for Spartan-6 user designs,it was missing in 3.2 release
  • CR 531463
  • Optimized the BUFR pin allocation rules to improve pin allocation efficiency for Virtex-6 DDR2/DDR3 x4 memory partdesigns
  • CR 531275
  • MIG uses either SRCC-P or MRCC-P pin for BUFR allocation for Virtex-6 DDR2/DDR3 designs. Until 3.2 release it wasusing only MRCC-P pin
  • CR 531274
  • Resolved Data Mask check box issues in GUI for specific Virtex-4, Virtex-5 DDR/DDR2 RDIMM x4 memory parts
  • CR 531216
  • For Virtex-6 RLDRAM II designs tCK simulation violations for -18 parts at 370MHz frequency got resolved withfrequency to time period change in MIG GUI
  • CR 531188
  • For Virtex-6 RLDRAM II designs the description part of the notes section in bank selection page is updated forselected pin compatible FPGA selections
  • CR 531024
  • Removed extra string appears in Summary page of MIG GUI for Virtex-6 RLDRAM II designs
  • CR 531023
  • For Virtex-6 FF1156 package full vicinity box appears in bank selection page of MIG GUI for default bankselections. In older versions only part of the vicinity box appeared
  • CR 529718
  • Enabled only RTT (nominal) values for On Die Termination selection in MIG GUI for Virtex-6 DDR3 SDRAM designs aswe are not supporting multiple slot cases for now
  • CR 529179
  • Verify UCF checks for the distance between DQ and DQS signals to keep better timing
  • CR 525716
  • Removed UCF LOC constraints for EN_DQS flops as predictable IP is used to constrain these paths
  • CR 529678
  • Changed the MAXDELAY constraints in UCF file for Virtex-5 DDR2 SDRAM designs to fix false hold violations onunconstrained paths
  • CR 534675
  • Fixed the timing issues for Spartan designs
  • CR 533353

Known Issues

Spartan-6 FPGA MCB

  • (Xilinx Answer 34165) MIG v3.3, Spartan-6 FPGA MCB - Incorrect port connection causes Continuous DQS Tuning to behave incorrectly - Manual modification required
  • (Xilinx Answer 34046) MIG v3.3, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported
  • (Xilinx Answer 34055) MIG v3.3, Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?
  • (Xilinx Answer 34089) MIG v3.3, Spartan-6 FPGA MCB - Some bits of the MCB address bus (mcbx_dram_addr) may violate the input hold time (tIH) specification of the memory device
  • (Xilinx Answer 34137) MIG v3.3, Spartan-6 FPGA LPDDR - Drive strength selected in MIG is not properly set in the output design

Virtex-6 FPGA DDR2/DDR3 SDRAM

  • (Xilinx Answer 34204) MIG v3.0-3.3, Virtex-6 DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue
  • (Xilinx Answer 34445) MIG v3.3, Virtex-6 DDR3 - ODT not asserted properly during initial write leveling and timing calibration causes calibration to fail
  • (Xilinx Answer 34094) MIG v3.3, Virtex-6 FPGA DDR2/DDR3- MMCM CLKFBOUT_MULT_F= 4 not valid, manual modification required
    (Xilinx Answer 33957) MIG v3.3, Virtex-6 DDR3: ZQ Short Calibration Commands are not seen in simulation or hardware
  • (Xilinx Answer 33418) MIG v3.2, v3.3, Virtex-6 FPGA DDR3 - When targeting a RDIMM with CWL=7, the design does not drive the correct write data in OTF mode
  • (Xilinx Answer 33441) MIG v3.2, Virtex-6 DDR2/DDR3 - The periodic reads associated with the phase detector are not properly sent according to the tPRDI timing parameter
  • (Xilinx Answer 33803) MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - Read Modify Write command fails when using Data Mask to mask individual bytes.
  • (Xilinx Answer 33804) MIG v3.3, Virtex-6 FPGA, DDR2 - Timing parameter tRC min will be violated if CAS Latency (CL) is 4 for with 2T timing.
  • (Xilinx Answer 33807) MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - The VHDL traffic generator will hang after a few reads for designs with a Burst Length of 4.
  • (Xilinx Answer 33832) MIG v3.3, Virtex-6 DDR3 DIMM - MIG does not allocate two sets of CK/CK#, CS and ODT for data widths that two DIMMs
  • (Xilinx Answer 33995) MIG 3.3, Virtex-6 FPGA DDR3 - Write Leveling does not succeed and calibration fails due to IDELAYCTRL not being automatically inferred by the software

Virtex-6 FPGA QDRII+ SRAM

  • (Xilinx Answer 33289) MIG v3.1, v3.2, v3.3 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration
  • (Xilinx Answer 33831) MIG v3.3, Virtex-6 QDRII+ - Warning Messages are displayed in the Bank Selection terminal/console

Virtex-6 RLDRAMII

  • (Xilinx Answer 33377) MIG v3.2, v3.3, Virtex-6 FPGA RLDRAMII - Design is unroutable when Debug Signals are turned on

Spartan-6 FPGA MCB

Virtex-4 and Virtex-5 FPGA DDR/DDR2 SDRAM

  • (Xilinx Answer 33741) MIG v3.2, v3.3, Virtex-4/Virtex-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column

MIG Tool

  • (Xilinx Answer 32320) MIG v3.0, v3.1, v3.2, v3.3 - Issues can occur when generating/regenerating a MIG project with the same component name

Linked Answer Records

Child Answer Records

AR# 33706
Date Created 11/14/2009
Last Updated 05/22/2012
Status Active
Type Release Notes
IP
  • MIG