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AR# 33709 Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Improve Timing Closure

Description

Improvements made to the Block Plus Core Wrapper source file "pcie_ep.v" help timing closure. This file will be part of the v1.13 release in ISE Design Suite 11.4, but will also work with the v1.12 core in ISE Design Suite 11.3, and v1.11 core in ISE Design Suite 11.2.

Solution

In v1.12 and later, the wrapper source files are now delivered with the generated core. Place the "pcie_ep.v" file (found in the zip filebelow) in the directory: <generated_core_name>/source.

If you are using the v1.11 core, you will need to place the file into the folder:
C:\Xilinx\11.1\ISE\coregen\ip\xilinx\network\com\xilinx\ip\pcie_blk_plus_v1_11\pcie_top\

Or, a similar path for your installation.

Regenerate the v1.11 core from the CORE Generator software.

Thezip filecontaining the workaround is found at:
http://www.xilinx.com/txpatches/pub/applications/pci/ar33278_bp_v1_12_files.zip

Note that this zipfile contains workarounds for other issues in v1.12. Please see the "readme.txt" in the zipfile for more information.

This workaround file should not be used on cores prior to v1.11.

These fixes are scheduled to be included in the v1.13 Block Plus Core (included in ISE Design Suite 11.4).

Revision History
07/05/2011 - Updated title
10/26/2009 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33580 Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33580 Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record N/A N/A

Actions

AR# 33709
Date Created 10/23/2009
Last Updated 05/22/2012
Status Active
Type Design Advisory
IP
  • Virtex-5 Integrated Endpoint Block
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