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AR# 33714

11.4 EDK, MPMC v5.02.a - MPMC timing errors occur when using the VFBC PIM in Spartan-6 FPGA


When using the VFBC PIM of MPMC in Spartan-6 FPGA only, I receive multiple difficult timing errors which contain the p0_wr_count signal in the path. How do I resolve this issue?


This issue has been fixed in MPMC v5.04.a, to be released in EDK 11.4.

AR# 33714
Date 05/23/2014
Status Archive
Type General Article
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