This Answer Record contains the Release Notes for the LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) v1.1 Core, released in ISE Design Suite 11.4, and includes the following:
- General Information
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
- This is the initial release of the Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core.
The following are generated out of the CORE Generator software:
- Ten Gigabit Ethernet PCS/PMA (10GBASE-R) core netlist
- Example design HDL top-level and associated HDL files to connect to Virtex-6 FPGA HXT
- Demonstration test bench to exercise the example design
- Documentation directory containing Data Sheet and Users Guide
(Xilinx Answer 33782) LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) v1.1 - Incorrect logic resources reported in data sheet
(Xilinx Answer 33799) LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R) v1.1 - Failures occur when running NCSIM Verilog simulation due to a compilation error with v6gth_wrapper_gth_init.v wrapper file from the GTH wizard.
(Xilinx Answer 33802) Virtex-6 FPGA GTH Transceiver - GTHINIT must be reissued following completion of an initial reset sequence