AR #33740 - 11.3 Spartan-6/Virtex-6 FPGA MAP - IODELAYs are being auto-inserted for some paths in ISE software version 11.3 where they did not in 11.2.
11.3 Spartan-6/Virtex-6 FPGA MAP - IODELAYs are being auto-inserted for some paths in ISE software version 11.3 where they did not in 11.2.
| AR# | 33740 |
| Part | SW-Pack |
| Last Modified | 2009-11-03 00:00:00.0 |
| Status | Active |
| Keywords | IODELAY, delay, inserted, insertion, automatic, not working |
Description
Keywords: IODELAY, delay, inserted, insertion, automatic, not working
My design was working in ISE software 11.2, but does not work in 11.3. I have debugged the issue to an input FF in an ILOGIC component. The data path has an IODELAY inserted in it, whereas this did not happen in 11.2. Why has this changed?
Solution
A change was made in ISE software 11.3 so that IODELAYs were incorrectly inserted on the data path of input FFs when clocked from a DCM-->BUFG-->FLOP clock path. This change will be removed for ISE software 11.4. Meanwhile, the IODELAY insertion can be prevented by putting an IODELAY=NONE attribute on either the pad or pad net.Example UCF syntax to override auto-insertion of IODELAY components:
INST "pad_name" IODELAY=NONE;
NET "pad_net_name" IODELAY=NONE;