AR #33741 - MIG v3.2, Virtex-4/Virtex-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column
MIG v3.2, Virtex-4/Virtex-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column
| AR# | 33741 |
| Part | IP-MIG-DDR SDRAM |
| Last Modified | 2009-11-05 00:00:00.0 |
| Status | Active |
| Keywords | spreadsheet, xls, Memory Interface Generator, window, PLL, clk0, clk90 |
Description
Keywords: spreadsheet, xls, Memory Interface Generator, window, PLL, clk0, clk90
The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column.
Solution
The timing parameter for the PLL static offset, Tstaphaoffset, should be accounted for in both the Before and After DQS column of the spreadsheet write_data_timing.xls. In MIG 3.2, this parameter is only accounted for in the "Before DQS" column, while the "After DQS" column lists it's contribution as 0ps.This will be fixed in a future release of MIG. For now you must manually update the spreadsheet to use the same value listed in the "Before DQS" column in the "After DQS" column for the parameter Tstaphaoffset.