11.3 Virtex-6 FPGA MAP - Change in trimming behavior related to IBUFDS_GTXE1 components

AR#	33743	Search For Another Answer
Topic	Map
Last Updated	09/09/2010
Status	Active

Description

My PCIe design was working properly in ISE software 11.2, but fails in 11.3 with trimming issues related to some GTXE1 components. I am using Synplify Pro.

Is there a known problem in 11.3 that leads to this trimming?

Solution

This problem is related to the way the ISE tools handle IBUFDS_GTXE1 inputs that are connected directly to input ports. In 11.2, NGDBuild would automatically connect PADs to these IBUFDS_GTXE1 inputs and then MAP would automatically insert IBUFs between the PAD and IBUFDS_GTXE1 inputs. This behavior was changed for 11.3 because XST is now inserting IBUFs on the IBUFDS_GTXE1 inputs. This behavioral change overlooked the fact that Synplify Pro still passes IBUFDS_GTXE1s with input port connections, and so the new tool behavior does not work for these netlists. 

This problem is scheduled to be fixed by Synplicity in their December release (D--2009.12).

Meanwhile, to work around the issue, instantiate IBUFs between the input port and IBUFDS_GTXE1 inputs.