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AR# 33743

11.3 Virtex-6 FPGA MAP - Change in trimming behavior related to IBUFDS_GTXE1 components


My PCIe design was working properly in ISE software 11.2, but fails in 11.3 with trimming issues related to some GTXE1 components. I am using Synplify Pro.

Is there a known problem in 11.3 that leads to this trimming?


This problem is related to the way the ISE tools handle IBUFDS_GTXE1 inputs that are connected directly to input ports. In 11.2, NGDBuild would automatically connect PADs to these IBUFDS_GTXE1inputs and thenMAP would automatically insert IBUFs between the PAD and IBUFDS_GTXE1 inputs. This behavior was changed for 11.3 because XST is now inserting IBUFs on the IBUFDS_GTXE1 inputs. This behavioral change overlooked the fact that Synplify Pro still passes IBUFDS_GTXE1s withinput port connections,and sothe new tool behavior does not work for these netlists.
This problem is scheduled to be fixed by Synplicity in their December release (D--2009.12).
Meanwhile, to work around the issue, instantiate IBUFs between the input port and IBUFDS_GTXE1 inputs.
AR# 33743
Date 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
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