AR #33744 - 11.3 Virtex-5 FPGA MAP - Logic corruption related to combination of Global Opt options
11.3 Virtex-5 FPGA MAP - Logic corruption related to combination of Global Opt options
| AR# | 33744 |
| Part | SW-MAP |
| Last Modified | 2009-11-03 00:00:00.0 |
| Status | Active |
| Keywords | global opt, options, ERROR:MapLib:979 |
Description
Keywords: global opt, options, ERROR:MapLib:979
My design runs correctly with default options, but when I use the Global Optimization feature I see the following error. Why does this occur?
ERROR:MapLib:979 - LUT6 symbol "lut129501_7251" (output signal=lut129501_7251)
has input signal "lut129499_7249" which will be trimmed. See Section 5 of the
Map Report File for details about why the input signal will become undriven.
Solution
A case has been seen where Global Optimization corrupted the logic of a design by creating FFs with no input signal. This condition led to the MapLib:979 trimming error. It is possible that a similar logic corruption could result in logic corruption that does not trigger an error condition. This problem is under investigation. So far it appears that it only occurs when the following three options are used together. It is possible to use any two of these options together without problems.-global_opt speed
-retiming on
-equivalent_register_removal on