Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Image Statistics.

The following information is listed for each version of the core:

• New Features
• Bug Fixes
• Known Issues

Solution

General LogiCORE IP Image Statistics Issues

• (Xilinx Answer 34828) How do I simulate my Video IP pCore in EDK?

LogiCORE IP Image Statistics v5.01.a

There is an ISE Design Suite and EDK v5.01.a Rev1 patch available in (Xilinx Answer 58552). This patch was intended to fix issues listed below as (Xilinx Answer 58551).

• Initial release in ISE Design Suite 14.3, Vivado 2012.3

• All 7 series devices
• All Virtex-6 devices
• All Spartan-6 devices

Supported Devices (Vivado)

• All 7 series devices

New Features

• Fixed clock domain issues with registers in the AXI4-Lite connection
• Added a STATUS bit to alert the user when the Block RAMs have cleared

Resolved Issues (ISE)

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Resolved Issues (Vivado)

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Known Issues (ISE)

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?
• (Xilinx Answer 55980) Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?
• (Xilinx Answer 58551) Why do the YCrCb histogram results appear to be in the wrong bin location?
• (Xilinx Answer 60219) Why is the Image Statistics core histogram output less than the total number of pixels in the image?

Known Issues (Vivado)

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?
• (Xilinx Answer 55980) Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?
• (Xilinx Answer 58551) Why do the YCrCb histogram results appear to be in the wrong bin location?
• (Xilinx Answer 60219) Why is the Image Statistics core histogram output less than the total number of pixels in the image?

LogiCORE IP Image Statistics v5.00.a

• Initial release in ISE Design Suite 14.2, Vivado 2012.2

Supported Devices (ISE)

• All 7 series devices
• All Virtex-6 devices
• All Spartan-6 devices

Supported Devices (Vivado)

• All 7 series devices

New Features

• Separate clock domains between AXI4-Lite and AXI4-Stream

Bug Fixes

• N/A

Known Issues (ISE)

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Known Issues (Vivado)

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

LogiCORE IP Image Statistics v4.00.a

• Initial release in ISE Design Suite 14.1, Vivado 2012.1

Supported Devices (ISE)

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000
• Virtex-6
• Spartan-6

Supported Devices (Vivado)

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000

New Features

• ISE 14.1 Design Suite support
• AXI4-Stream data interfaces
• Optional AXI4-Lite control interface
• Built-in, optional bypass and test-pattern generator mode
• Built-in, optional throughput monitors
• Supports spatial resolutions from 32x32 up to 7680x7680
• Supports 1080P60 in all supported device families
• Supports 4kx2k @ 24 Hz in supported high performance devices

Bug Fixes

• N/A

Known Issues

• N/A

LogiCORE IP Image Statistics v3.0

• Initial release in ISE Design Suite 13.3

Supported Devices

• Virtex-7
• Virtex-7 XT (7vx485t)
• Virtex-7 -2L
• Kintex-7
• Kintex-7 -2
• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Spartan-6 XC LX/LXT
• Spartan-6 XA
• Spartan-6 XQ LX/LXT
• Spartan-6 -1L XC LX

New Features

• ISE 13.3 design tool support
• Virtex-7 and Kintex-7 support
• AXI4-Lite bus interface support for the EDK Pcore interface

Bug Fixes

• (Xilinx Answer 33848) Why do I receive Block RAM Collision errors in my simulation?
• (Xilinx Answer 41135) Why are the power, sum, min, max, hifreq, lofreq and edge signals not resetting after READOUT is deasserted?

Known Issues

• N/A

LogiCORE IP Image Statistics v2.0

• Initial release in ISE Design Suite 13.1

Supported Devices

• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Spartan-6 XC LX/LXT
• Spartan-6 XA
• Spartan-6 XQ LX/LXT
• Spartan-6 -1L XC LX
• Virtex-5 XC LX/LXT/SXT/TXT/FXT
• Virtex-5 XQ LX/ LXT/SXT/FXT
• Spartan-3A DSP

New Features

• ISE 13.1 design tool support

Bug Fixes

• CR 587266 - Low-pass filter quantization issues - edge-content incorrect
• CR 587079 - Last histogram bin (bin 255) incorrect
• CR 586692 - Data Valid - Addr Valid handshaking
• CR 586691 - Sum, Power, Freq and Edge outputs are not correctly initialized between frames
• (Xilinx Answer 40266) Why do the POW and SUM outputs toggle when DATA_VALID is asserted?
  CR 586690 - sum, power, edge, and frequency output values instable during readout phase
• CR 582199 - Image Statistics v1.0 - CORE Gen GUI Symbol always has the H_BLANK_IN, V_BLANK_IN and ACTIVE_VIDEO grayed out
• CR 581253 - HW Eval and Simulation license cause the CE to not work properly in simulation
• CR 553810 - Core Generation Info attribute contains wrong data
• CR 548340 - Coregen is running the generation flow twice
• CR 553988 - Image Statistics v1.0 - Can not modify parameterization from within EDK, like most IP, including the Video Analytics cores like the OSD and Video Scaler
• (Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
• (Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?
• (Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.

Known Issues

• (Xilinx Answer 33848) Why do I receive Block RAM Collision errors in my simulation?
• (Xilinx Answer 37987) Where can I find UG762: Xilinx Streaming Video Interface User Guide?
• (Xilinx Answer 41135) Why are the power, sum, min, max, hifreq, lofreq and edge signals not resetting after READOUT is deasserted?

LogiCORE IP Image Statistics v1.0

• Initial release in ISE Design Suite 11.4

New Features

• Support for:
  • High-definition (1080p60) resolutions
  • Up to 4096 total pixels and 4096 total rows
• Selectable processor interface
  • EDK pCore
  • General Purpose Processor
• 16 programmable zones
• 8, 10, or 12-bit input precision
• Outputs for all zones and color channels:
  • Minimum and maximum color values
  • Sum and sum of squares for each color value
  • Low and high frequency content
  • Horizontal, vertical and diagonal edge content
• Outputs for pre-selected zone(s):
  • Y channel histogram
  • R,G,B channel histograms
  • Two-dimensional Cr-Cb histogram
• Support for Virtex-5, Virtex-6, Spartan-3A DSP and Spartan-6 FPGAs
• ISE 11.4 design tools support

Bug Fixes

• N/A

Known Issues

• (Xilinx Answer 33848) Why do I receive Block RAM Collision errors in my simulation?
• (Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
• (Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.
• (Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?
• (Xilinx Answer 37987) Where can I find UG762: Xilinx Streaming Video Interface User Guide?
• (Xilinx Answer 40266) Why do the POW and SUM outputs toggle when DATA_VALID is asserted?

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