This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Image Statistics.
The following information is listed for each version of the core:
Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1.
Please contact Xylon, our IP partner, for solutions related to image statistics.
General LogiCORE IP Image Statistics Issues
| (Xilinx Answer 34828) | How do I simulate my Video IP pCore in EDK? |
LogiCORE IP Image Statistics v5.01.a
There is an ISE Design Suite and EDK v5.01.a Rev1 patch available in (Xilinx Answer 58552). This patch was intended to fix issues listed below as (Xilinx Answer 58551).
Supported Devices (Vivado)
New Features
Resolved Issues (ISE)
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
Resolved Issues (Vivado)
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
Known Issues (ISE)
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 55980) | Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? |
| (Xilinx Answer 58551) | Why do the YCrCb histogram results appear to be in the wrong bin location? |
| (Xilinx Answer 60219) | Why is the Image Statistics core histogram output less than the total number of pixels in the image? |
Known Issues (Vivado)
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 55980) | Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock? |
| (Xilinx Answer 58551) | Why do the YCrCb histogram results appear to be in the wrong bin location? |
| (Xilinx Answer 60219) | Why is the Image Statistics core histogram output less than the total number of pixels in the image? |
LogiCORE IP Image Statistics v5.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues (ISE)
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
Known Issues (Vivado)
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
LogiCORE IP Image Statistics v4.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues
LogiCORE IP Image Statistics v3.0
Supported Devices
New Features
Bug Fixes
| (Xilinx Answer 33848) | Why do I receive Block RAM Collision errors in my simulation? |
| (Xilinx Answer 41135) | Why are the power, sum, min, max, hifreq, lofreq and edge signals not resetting after READOUT is deasserted? |
Known Issues
LogiCORE IP Image Statistics v2.0
Supported Devices
New Features
Bug Fixes
| (Xilinx Answer 40266) | Why do the POW and SUM outputs toggle when DATA_VALID is asserted? |
| (Xilinx Answer 33872) | "ERROR: simAn IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: simError: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core. |
Known Issues
| (Xilinx Answer 33848) | Why do I receive Block RAM Collision errors in my simulation? |
| (Xilinx Answer 37987) | Where can I find UG762: Xilinx Streaming Video Interface User Guide? |
| (Xilinx Answer 41135) | Why are the power, sum, min, max, hifreq, lofreq and edge signals not resetting after READOUT is deasserted? |
LogiCORE IP Image Statistics v1.0
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 33848) | Why do I receive Block RAM Collision errors in my simulation? |
| (Xilinx Answer 33872) | "ERROR: simAn IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR: simError: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core. |
| (Xilinx Answer 35437) | Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name? |
| (Xilinx Answer 37987) | Where can I find UG762: Xilinx Streaming Video Interface User Guide? |
| (Xilinx Answer 40266) | Why do the POW and SUM outputs toggle when DATA_VALID is asserted? |
| AR# 33748 | |
|---|---|
| Date | 08/03/2018 |
| Status | Archive |
| Type | Release Notes |
| IP |
|