UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33749

LogiCORE IP Image Edge Enhancement - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Image Edge Enhancement.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP Image Edge Enhancement Lounge:
http://www.xilinx.com/products/ipcenter/EF-DI-IMG-ENHANCE.htm

Solution

General LogiCORE IP Image Edge Enhancement Issues

LogiCORE IP Image Edge Enhancement v6.00.a
  • Initial release in ISE 14.4and Vivado 2012.4 design tools
Supported Devices (ISE)
  • All 7 series devices
  • All Virtex-6 devices
  • All Spartan-6 devices
Supported Devices (Vivado)
  • All 7 series devices
New Features
  • Increase gain quantization from 1/4 to 1/16
Resolved Issues (ISE)
  • N/A
Resolved Issues (Vivado)
  • N/A
Known Issues (ISE)
  • (Xilinx Answer 57773) Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?
Known Issues (Vivado)
  • (Xilinx Answer 52215) Why does my core fail timing with a Critical Warning?
  • (Xilinx Answer 57773) Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?


LogiCORE IP Image Edge Enhancement v5.01.a

  • Initial release in ISE 14.3 and Vivado 2012.3 design tools
Supported Devices (ISE)
  • All 7 series devices
  • All Virtex-6 devices
  • All Spartan-6 devices
Supported Devices (Vivado)
  • All 7 series devices
New Features
  • Fixed clock domain issues with registers in the AXI4-Lite connection
Resolved Issues (ISE)
  • (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?
Resolved Issues (Vivado)
  • (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?
Known Issues (ISE)
  • (Xilinx Answer 60173) Why does the Image Enhancement core output data in the wrong columns after changing the number of columns via the AXI4-Lite interface?
  • (Xilinx Answer 57773) Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?
Known Issues (Vivado)
  • (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?
  • (Xilinx Answer 60173) Why does the Image Enhancement core output data in the wrong columns after changing the number of columns via the AXI4-Lite interface?
  • (Xilinx Answer 57773) Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation?


LogiCORE IP Image Edge Enhancement v5.00.a

  • Initial Release in ISE Design Suite 14.2, Vivado 2012.2
Supported Devices (ISE)
  • All 7 Series Devices
  • All Virtex-6 Devices
  • All Spartan-6 Devices
Supported Devices (Vivado)
  • All 7 Series Devices
New Features
  • ISE 14.2 software support
  • Added s_axi_aclk, s_axi_aclken, s_axi_aresetn to AXI4-Lite interface
Bug Fixes
  • N/A
Known Issues (ISE)
  • (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?
Known Issues (Vivado)
  • (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

LogiCORE IP Image Edge Enhancement v4.00.a
  • Initial Release in ISE Design Suite 14.1, Vivado 2012.1
Supported Devices (ISE)
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Virtex-6
  • Spartan-6
Supported Devices (Vivado)
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
New Features
  • ISE 14.1 software support
  • AXI4-Stream data interfaces
  • Optional AXI4-Lite control interface
  • Built-in, optional bypass and test-pattern generator mode
  • Built-in, optional throughput monitors
  • Supports spatial resolutions from 32x32 up to 7680x7680
  • Supports 1080P60 in all supported device families
  • Supports 4kx2k @ 24 Hz in supported high performance devices
Bug Fixes
  • N/A
Known Issues
  • N/A

LogiCORE IP Image Edge Enhancement v3.0
  • Initial Release in ISE Design Suite 13.3
Supported Devices
  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
New Features
  • ISE 13.3 software support
  • Virtex-7 and Kintex-7 device support
  • AXI4-Lite bus interface support for the EDK Pcore interface
Bug Fixes
  • (Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
  • (Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWritersUG:380 - The design contains secured core.
  • (Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?
Known Issues
  • N/A

LogiCORE IP Image Edge Enhancement v2.0
  • Initial Release in ISE Design Suite 12.4
New Features
  • New EDK pCore API functions
  • New STATUS register/port
  • ISE 12.4 software support
Bug Fixes
  • (Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
  • (Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.
  • (Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?
Known Issues
  • N/A

LogiCORE IP Image Edge Enhancement v1.0
  • Initial Release in ISE Design Suite 11.4
New Features
  • Support for:
    • High-definition (1080p60) resolutions
    • Up to 4096 total pixels and 4096 total rows
  • Programmable gain for edge directions
  • Selectable processor interface
    • EDK pCore
    • General Purpose Processor
    • Constant Interface
  • Support for 8, 10, or 12-bit input and output precision
  • YCrCb 444 input and output
  • Support for Virtex-5, Virtex-6, Spartan-3A DSP and Spartan-6 FPGAs
  • ISE 11.4 software support
Bug Fixes
  • N/A
Known Issues
  • (Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
  • (Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.
  • (Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?
  • (Xilinx Answer 37987) Where can I find the Xilinx Streaming Video Interface User Guide(UG762)?

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 33749
Date Created 11/13/2009
Last Updated 04/29/2014
Status Active
Type Release Notes
IP
  • Image Enhancement