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AR# 33750

LogiCORE IP Image Noise Reduction - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP Image Noise Reduction.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP Image Noise Reduction Lounge:

http://www.xilinx.com/products/ipcenter/EF-DI-IMG-NOISE.htm

Note: This core has been superseded by the LogiCORE Image Enhancement core released in Vivado Design Suite 2013.2 and will be removed from the IP catalog as of 2014.1.
As of June 2014, no new licenses will be issues and after June 2015, support will no longer be available.

Solution

General LogiCORE IP Image Noise Reduction Issues
LogiCORE IP Image Noise Reduction v5.01.a
  • Initial release in ISE Design Suite 14.3, Vivado 2012.3
Supported Devices (ISE)
  • All 7 series devices
  • All Virtex-6 devices
  • All Spartan-6 devices
Supported Devices (Vivado)
  • All 7 series devices
New Features
  • Fixed clock domain issues with registers in the AXI4-Lite connection
Resolved Issues (ISE)

(Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Resolved Issues (Vivado)
 
(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Known Issues (ISE)

(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

Known Issues (Vivado)
 
(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

LogiCORE IP Image Noise Reduction v5.00.a
  • Initial release in ISE Design Suite 14.2, Vivado 2012.2
Supported Devices (ISE)
  • All 7 series devices
  • All Virtex-6 devices
  • All Spartan-6 devices
Supported Devices (Vivado)
  • All 7 series devices
New Features
  • ISE 14.2 design tool support
  • Added s_axi_aclk, s_axi_aclken, s_axi_aresetn to AXI4-Lite interface
Bug Fixes
  • N/A
Known Issues (ISE)

(Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?
Known Issues (Vivado)
 
(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

LogiCORE IP Image Noise Reduction v4.00.a
  • Initial release in ISE Design Suite 14.1, Vivado 2012.1
Supported Devices (ISE)
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Virtex-6
  • Spartan-6
Supported Devices (Vivado)
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
New Features
  • ISE 14.1 design tool support
  • AXI4-Stream data interfaces
  • Optional AXI4-Lite control interface
  • Built-in, optional bypass and test-pattern generator mode
  • Built-in, optional throughput monitors
  • Supports spatial resolutions from 32x32 up to 7680x7680
  • Supports 1080P60 in all supported device families
  • Supports 4kx2k @ 24 Hz in supported high performance devices
Bug Fixes
  • N/A
Known Issues
  • N/A
LogiCORE IP Image Noise Reduction v3.0
  • Initial release in ISE Design Suite 13.3
Supported Devices
  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
New Features
  • ISE 13.3 design tool support
  • Virtex-7 and Kintex-7 support
  • AXI4-Lite bus interface support for the EDK Pcore interface
Bug Fixes

(Xilinx Answer 33913) Why does generation fail when I try to use "noise" for the Component Name?
(Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
(Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.
(Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?
Known Issues

(Xilinx Answer 46301) Why does the output image look like it is and overlapping version of the input image?

LogiCORE IP Image Noise Reduction v2.0
  • Initial release in ISE Design Suite 12.4
New Features
  • New EDK pCore API functions
  • New option to pass data through without filtering
  • New STATUS register/port
  • ISE 12.4 design tool support
Bug Fixes
 
(Xilinx Answer 33913) Why does generation fail when I try to use "noise" for the Component Name?
(Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
(Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.
(Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?

Known Issues
 
(Xilinx Answer 46301) Why does the output image look like it is and overlapping version of the input image?

LogiCORE IP Image Noise Reduction v1.0
  • Initial release in ISE Design Suite 11.4
New Features

  • Support for:
    • High-definition (1080p60) resolutions
    • Up to 4096 total pixels and 4096 total rows
  • In-system update of smoothing filters
  • Selectable processor interface
    • EDK pcore
    • General Purpose Processor
    • Constant Interface
  • Support for 8, 10, or 12-bit input and output precision
  • YCrCb 444 input and output
  • Support for Virtex-5, Virtex-6, Spartan-3A DSP and Spartan-6 devices
  • ISE 11.4 design tool support
Bug Fixes
  • N/A
Known Issues
 
(Xilinx Answer 33913) Why does generation fail when I try to use "noise" for the Component Name?
(Xilinx Answer 33872) "ERROR: sim - An IP generation script exited abnormally. Error found during generation."
(Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR: sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.
(Xilinx Answer 35437) Why do I see an error saying my core failed to generate on Linux, when there is an uppercase letter in the component name?
(Xilinx Answer 37987) Where can I find UG762: Xilinx Streaming Video Interface User Guide?
(Xilinx Answer 46301) Why does the output image look like it is and overlapping version of the input image?

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 33750
Date Created 11/03/2009
Last Updated 09/03/2015
Status Active
Type Release Notes
IP
  • Image Noise Reduction