• (Xilinx Answer 34828) How do I simulate my Video IP pCore in EDK?

LogiCORE IP Motion Adaptive Noise Reduction v5.00.a

• Initial Release in ISE Design Suite 14.2, Vivado 2012.2

Supported Devices (ISE)

• All 7 Series Devices
• All Virtex-6 Devices
• All Spartan-6 Devices

Supported Devices (Vivado)

• All 7 Series Devices

New Features

• Inclusion of AXI4Lite clock and reset.
• AXI4Lite <-> Other domain CDC now to be handled in the core, not the interconnect
  

Bug Fixes

• N/A

Known Issues (ISE)

• N/A

Known Issues (Vivado)

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?

LogiCORE IP Motion Adaptive Noise Reduction v4.00.a

• Initial Release in ISE Design Suite 14.1, Vivado 2012.1

Supported Devices (ISE)

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000
• Virtex-6
• Spartan-6

Supported Devices (Vivado)

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000

New Features

• ISE 14.1 Design Suite support
• Virtex-7, Kintex-7, Artix-7 and Zynq support
• Video over AXI4-Stream interface support for the input and output interfaces
• AXI4-Lite bus interface support for the processor interface
• Separate AXI4Stream output interface for Motion.
• Independent Chroma Motion Transfer Function table
• 5 Preloaded MTF tables.
  

Bug Fixes

• N/A

Known Issues

• N/A

LogiCORE IP Motion Adaptive Noise Reduction v2.0

• Initial Release in ISE Design Suite 13.1

• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Spartan-6 XC LX/LXT
• Spartan-6 XA
• Spartan-6 XQ LX/LXT
• Spartan-6 -1L XC LX
• Virtex-5 XC LX/LXT/SXT/TXT/FXT
• Virtex-5 XQ LX/ LXT/SXT/FXT
• Spartan-3A DSP

• Added AXI Lite interface to pCore, removing the PLB interface.

• Made the VFBC interface available for GPP core.

• N/A

LogiCORE IP Motion Adaptive Noise Reduction v1.1

There was a v1.1 rev1 patch available in (Xilinx Answer 35313). This patch was intended to fix issues listed below as (Xilinx Answer 38597).

• Initial Release in ISE Design Suite 12.3

• Core Version register added
• ISE 12.3 software support

• (Xilinx Answer 35395) Spartan-6 FPGA core should only be generated in ISE 12.1 design tools and later due to potential block RAM memory related problems
• CR566512 Core not generated correctly - XMANR.vhd not being delivered.

• (Xilinx Answer 38597) Why is the Motion Adaptive Noise Reduction so large when using the pCore interface?

LogiCORE IP Motion Adaptive Noise Reduction v1.0

• Initial Release in ISE Design Suite 11.4

• ISE 11.4 software support
• Initial release

• N/A

• (Xilinx Answer 35395) Spartan-6 FPGA core should only be generated in ISE 12.1 design tools and later due to potential block RAM memory related problems