AR #33757 - HW SelectIO technology - Implementation tools do not allow I/O pins with the I/O standard SSTL2_II to be assigned to Spartan-6 FPGA Bank 0 or Bank 2
HW SelectIO technology - Implementation tools do not allow I/O pins with the I/O standard SSTL2_II to be assigned to Spartan-6 FPGA Bank 0 or Bank 2
| AR# | 33757 |
| Part | HW-SelectIO |
| Last Modified | 2009-11-05 00:00:00.0 |
| Status | Active |
| Keywords |
Description
The implementation tool will not allow I/O pins with the I/O standard SSTL2_II to be assigned to a Spartan-6 FPGA Bank 0 or Bank 2. It gives the following error:
ERROR:Place:1333 - Following IOB's that have input/output programming are locked
to the bank 2 that does not support such values
IO Standard: Name = SSTL2_II, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
OUTPUT, DRIVE_STR = NR ...
Why is this configuration not supported?
Solution
Assuming all other banking rules are satisfied, there is no physical restriction to having SSTL2_II standards in bank 0 or 2. This is a software issue that will be resolved in the 12.1i release of the tools. If a design requires Bank 0 or 2 to have SSTL2_II standard, please open a webcase with the technical support group: http://www.xilinx.com/support/Banking rules for Spartan-6 FPGA can be found here:
http://www.xilinx.com/support/documentation/user_guides/ug361.pdf see ?Rules for Combining I/O Standards in the Same Bank?