We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 33757

HW SelectIO technology - Implementation tools do not allow I/O pins with the I/O standard SSTL2_II to be assigned to Spartan-6 FPGA Bank 0 or Bank 2


The implementation tool does not allow I/O pins with the I/O standard SSTL2_II to be assigned to a Spartan-6 FPGA Bank 0 or Bank 2 and results inthe following error:

"ERROR:Place:1333 - Following IOB's that have input/output programming are lockedto the bank 2 that does not support such valuesIO Standard: Name = SSTL2_II, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =OUTPUT, DRIVE_STR = NR ..."

Why is this configuration not supported?


Assuming that all other banking rules are satisfied, there is no physical restriction to having SSTL2_II standards in Bank 0 or 2. This is a software issue that is scheduled to be resolved in the 12.1 release of the tools. If a design requires Bank 0 or 2 to have SSTL2_II standard, please open a WebCase with Technical Support: http://www.xilinx.com/support/

Banking rules for Spartan-6 FPGA can be found at:

See "Rules for Combining I/O Standards in the Same Bank."

AR# 33757
Date 12/15/2012
Status Active
Type General Article