Description

This answer record contains the Release Notes and Known Issues list for the LogiCORE IP Peak Cancelation Crest Factor Reduction Core.

The following information is listed for each version of the core:

• General Information
• New Features
• Supported Devices
• Resolved Issues
• Known Issues

LogiCORE IP Peak Cancellation Crest Factor Reduction Lounge:
http://www.xilinx.com/products/ipcenter/EF-DI-PC-CFR.htm

Solution

LogiCORE IP Peak Cancellation Crest Factor Reduction v3.1

New Features

• ISE 14.4 design tools support
• Vivado 2012.4 tool support
• Multiple CPGs per iteration support (1 to 12)
• Introduction of Peak Detect Window in place of Allocator Spacing
• Support for Real and Complex CP coefficients

• Zynq-7000
• All 7 series devices
• All Virtex-6 devices

• Zynq-7000
• All 7 series devices

• When using ISE v12.3 design tools the PC_CFR does not function correctly. Why? See (Xilinx Answer 39276).
• The data sheet does not show the latency for the core. How do I determine the latency? (Xilinx Answer 36855).
• Is the reconfigurable coefficients variant of the PC-CFR is affected by the Spartan-6 FPGA block RAM issue? (Xilinx Answer 37280).
• What do we need to check if configurable coefficients do not seem to work? (Xilinx Answer 37477).

• None

• (Xilinx Answer 53465) 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with error "Error: Failed to find design work Core name"?

LogiCORE IP Peak Cancellation Crest Factor Reduction v3.0

New Features

• ISE 13.2 design tools support
• Multiple antenna support (1, 2, 4 and 8)
• Multiple iteration support (1 to 8)
• AXI support
• I/O quantization support (11 to 18)
• Tx bandwidth support up to 145 MHz
• LTE 40 MHz channel support
• Latency control through GUI
• Filter length up to 2047 supported
• C model

Supported Devices

• Zynq-7000*
• Virtex-7
• Virtex-7 XT (7vx485t)
• Virtex-7 -1L
• Kintex-7
• Kintex-7 -1L
• Artix-7*
• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Virtex-6 -1L XQ LXT/SXT
• Spartan-6 XC LX/LXT
• Spartan-6 XQ LX/LXT
• Spartan-6 -1L XC LX
• Spartan-6 -1L XQ LX

*To access these devices in the ISE Design Suite, contact your Xilinx FAE.

Resolved Issues

• When using ISE v12.3 design tools the PC_CFR does not function correctly. Why? See (Xilinx Answer 39276).
• The data sheet does not show the latency for the core. How do I determine the latency? (Xilinx Answer 36855).
• Is the reconfigurable coefficients variant of the PC-CFR is affected by the Spartan-6 FPGA block RAM issue? (Xilinx Answer 37280).
• What do we need to check if configurable coefficients do not seem to work? (Xilinx Answer 37477).

Known Issues (ISE)

• None

Known Issues (Vivado)

• None

LogiCORE IP Peak Cancelation Crest Factor Reduction v2.0

Initial Release in ISE Design Suite 11.4

New Features

• 11.4 ISE design tools support
• New core introduction

Resolved Issues

• None

Known Issues

• When using ISE v12.3 design tools, the PC_CFR does not function correctly. Why? See (Xilinx Answer 39276).
• The data sheet does not show the latency for the core. How do I determine the latency? (Xilinx Answer 36855).
• Is the reconfigurable coefficients variant of the PC-CFR affected by the Spartan-6 FPGA block RAM issue? (Xilinx Answer 37280).
• What do we need to check if configurable coefficients do not seem to work? (Xilinx Answer 37477).

Linked Answer Records

Master Answer Records

Child Answer Records