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AR# 33762 Endpoint Block Plus Wrapper v1.13 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4

This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.13, released in ISE Design Suite 11.4, and contains the following information:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

General Information

The LogiCORE Endpoint Block Plus for PCI Express is shipped with a free license. See (Xilinx Answer 33386) for more information.

The v1.12 and later core versions now include source code for the Block Plus wrapper that instantiates the integrated block for PCI Express. The wrapper source code is contained in the directory named <project_name>/source. An NGC file is no longer delivered and the source code is synthesized as part of the user project. The synthesis scripts in the <project_name>/implement directory show examples of how to read in the source code for synthesis. Xilinx does not support any modifications made to the source code.

New Features

  • ISE 11.4 software support
  • Synplify support added
  • SX240T support added

Resolved Issues

CR530800: Un-checking TX_DIFF_BOOST checkbox causes core generation failure.

Issue resolved where Un-checking the TX_DIFF_BOOST checkbox during the Core customization process was causing the Core generation to fail.

CR529525: ISE Proj Nav flow

Issue resolved where `defines for module names have been removed from the Example design delivered with the core, as this was not compatible with the ISE Proj Nav flow.

CR537266: XCF Files delivered

Issue resolved where XCF files were not delivered with the core. This caused difficulty in timing closure.

CR483369: implement_dual.bat now delivered

The implement_dual.bat script is now delivered.

CR536473: trn_rnp_ok_n deassertion causing Posted & Completion transactions to stall

Issue resolved where trn_rnp_ok_n deassertion for an extended period of time caused Posted & Completion transactions to stall.

CR532483: Polarity reversal on Lane 7 not detected.

Issue resolved where the core was not detecting Polarity reversal on Lane 7, in an 8-lane product.

CR529523: Core Transmit interface lock up after warm reset.

Issue resolved where the core transaction transmit interface would lock up after a warm reset because of the Calendar logic's failure to capture initial data correctly.

CR529524: Synplify support now available

Support for Synplify is now available.

Known Issues

There are three main components to the Endpoint Block Plus Wrapper for PCI Express:

  • Virtex-5 FPGA Integrated Block for PCI Express
  • Virtex-5 FPGA GTP/GTX Transceivers
  • Block Plus Wrapper FPGA fabric logic

The known issues for the integrated block and GTP/GTX transceivers are found in the Block Plus core user guide delivered with the core and found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

Block Plus Wrapper FPGA fabric logic

(Xilinx Answer 31646) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual Core UCF problems

(Xilinx Answer 33643) - Endpoint Block Plus Wrapper v1.12 for PCI Express - Cannot implement the core in Project Navigator

(Xilinx Answer 33826) - Endpoint Block Plus Wrapper v1.13 for PCI Express - When Generating for Synplicity Flow Using VHDL, the implement.sh file is Not Calling XST to Synthesize Wrapper

(Xilinx Answer 33827) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Warning Messages during Core Generation

(Xilinx Answer 33847) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Incorrect voltage swing when GT_TX_BUFFCTRL is left unconnected in top level core file

(Xilinx Answer 33918) Virtex-6, Spartan-6 FPGA and Block Plus Integrated Block Wrappers for PCI Express- Why is the root port model and testbench provided with the example simulation not passing Memory or I/O transactions to the user side interface?

(Xilinx Answer 33937) - Endpoint Block Plus Wrapper for PCI Express - The implement.sh[bat] file errors our during synthesis of the wrapper files

(Xilinx Answer 33827) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Warning Messages appear in the CORE Generator tool

(Xilinx Answer 33850) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Reading and Writing Configuration Space Registers Fails

(Xilinx Answer 34444) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Transmit Stall Due to Link Partner Advertisement of Data Limited Completion Credits

(Xilinx Answer 34706) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Disconnecting Packets on TX Interface when Interfacing with a link Partner Advertising Non-Infinite Completion Credits May Eventually Stall the Transmit Interface

(Xilinx Answer 34707) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Cannot Change Default Pre-Emphasis (TXPREEMPHASIS)

(Xilinx Answer 34710) - Endpoint Block Plus Wrapper v1.13 for PCI Express - Extensive deassertion of trn_rnp_ok_n could lock up receive interface

Revision History
03/16/2010 - Added 33827, 34706, 34707, 34710
02/24/2010 - Added 34444
01/19/2010 - Added 33850
12/09/2009 - Added 33918 and 33937
12/07/2009 - Added 33847
12/02/2009 - Initial Release

AR# 33762
Date Created 11/13/2009
Last Updated 03/16/2010
Status Active
Type
Devices
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
IP
  • Endpoint Block Plus Wrapper for PCI Express
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