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AR# 33769

LogiCORE IP Tri-Mode Ethernet MAC v4.3 - CE incorrectly timed for DDR primitives in Spartan-6 FPGA designs


The CE input to the Spartan-6 FPGA DDR primitives is incorrectly timed against both clock edges irrespective of the DDR_ALIGNMENT attribute.


To avoid this issue the ucf can be updated to add the following Datapathonly constraint to cover this path.

INST "*rgmii_interface?control_enable" TNM = "ddr_control";

TIMESPEC "TS_ddr_control" = FROM "ddr_control" 6800 ps DATAPATHONLY;

This constraint identifies the path from the control enable register as this is only used to drive the CE input.

The ucf has been updated in the Tri-Mode Ethernet MACv4.3 rev1 patch. To get the patch see:

(Xilinx Answer 33307) LogiCORE IP Tri-Mode Ethernet MAC v4.3 - Release Notes and Known Issues for ISE 11.3

AR# 33769
Date Created 11/09/2009
Last Updated 12/15/2012
Status Active
Type General Article