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AR# 3377

EXEMPLAR: Instantiating a pulldown/pullup in Verilog?

Description


Urgency: Standard



General Description:

Xilinx FPGAs contain internal pullup resistors in the I/O blocks (some also contain pulldowns). These components can be instantiated in Exemplar's Verilog code.

Solution


Below is an example (from Exemplar) that illustrates how to instantiate pullups in a verilog file:



module test (a, oe, o);

inout [2:0] a ;

input [3:0] oe ;

inout o ;



wire bus;

assign bus = oe[2] ? a[2] : 'bz;

assign bus = oe[1] ? a[1] : 'bz;

assign bus = oe[0] ? a[0] : 'bz;

PULLUP i0 (.O(bus));

PULLUP i1 (.O(a[0]));

assign o = oe[3] ? bus : 'bz;



endmodule







Note: For CPLD devices, PULLUPs in the IOBs are not user controllable during normal operation. These PULLUP resistors are active only during device programming, power-up, and erase cycle.
AR# 3377
Date Created 08/31/2007
Last Updated 08/28/2011
Status Archive
Type General Article