The 4.3 release of the core had not been verified in hardware for Spartan-6.
The RGMII I/O logic was therefore based upon static timing and timing simulation results both of which are based on pre-production speed files.
On further testing updates to the I/O logic are needed.
The IODELAY2 usage needs to be replaced with a DCM.
The core has been updated in the Tri-Mode Ethernet MACv4.3 rev1 patch to use a DCM for RGMII when targeting a Spartan-6 FPGA.
See the tri_mode_eth_mac_v4_3_rev1.pdf provided in the patch for more details including updated clocking diagrams.
To get the patch see:
(Xilinx Answer 33307) LogiCORE IP Tri-Mode Ethernet MAC v4.3 - Release Notes and Known Issues for ISE 11.3