Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express
Description
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
Solution
For a list of all current Release Notes and Known Issues for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express, please refer to the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
Design Advisories
02/02/2012 - (Xilinx Answer 45771) - Design Advisory for the Virtex-6 Integrated Block for PCI Express - The receive interface signal m_axis_rx_tvalid might deassert in the middle of a packet when using the 128-bit x8 Gen 2 interface
01/20/2011 - (Xilinx Answer 39456) - Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Delay Aligner Work-around
11/18/2010 - (Xilinx Answer 39164) - Design Advisory for the Virtex-6 Integrated Block Wrapper v1.6 and v2.1 for PCI Express - Need to set BANDWIDTH attribute on MMCM to Low
08/04/2010 - (Xilinx Answer 37207) - Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit Wrapper is Not Deasserting trn_tdst_rdy_n When Integrated Block Transmit Buffer is Full
To update your Xilinx Alert Notification Preferences, please go to: http://www.xilinx.com/support/myalerts
Revision History
02/02/2012 - Added 45771
07/05/2011 - Updated title
01/20/2011 - Added 39456
11/18/2010 - Added 39164
08/03/2010 - Added 37207
11/16/2009 - Added new link to access preferences.
11/09/2009 - Initial Release
Applies To
Devices
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
IP
- Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )