AR #33776 - Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express
Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express
| AR# | 33776 |
| Topic | IP-SysIO-PCI Express Block |
| Last Modified | 2009-11-18 00:00:00.0 |
| Status | Active |
Description
Keywords: Design Advisory, endpoint, PCIe
Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
Solution
For a list of all current Release Notes and Known Issues for the Spartan-6 FPGA Integrated Block Wrapper for PCI Express, please refer to the IP Release Notes Guide:http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
Design Advisories
(Xilinx Answer 33761) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to Enable use of a 100 MHz Reference Clock
(Xilinx Answer 33774) - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - 250 MHz Is Not a Valid Reference Clock Option
To update your Xilinx Alert Notification Preferences, please go to:
http://www.xilinx.com/support/myalerts
Revision History
11/16/2009 - Added new link to access preferences.
11/09/2009 - Initial Release; Added Answer Records 33761 and 33774.