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AR# 33783 11.3 Virtex-5 FPGA Place - Map crashes in placement Phase 9.30 after printing global clock distribution report

Description

Keywords: global, clock, distribution, 9.30, crash

My small design fails in Map resulting in a crash during placement Phase 9.30 just after the global clock distribution report is printed.

Are there any known issues in this area.

Solution

An issue has been seen where a crash occurs during Phase 9.30 after the global clock distribution report is printed. The crash is related to the use of an algorithm that is only enabled for low utilization designs. This problem can be avoided by disabling that algorithm with an environment variable:

Linux
setenv PAR_USE_LOWUTILHEUR 0

Windows
SET PAR_USE_LOWUTILHEUR=0

For general information about setting ISE software environment variables, see (Xilinx Answer 11630).

Actions

AR# 33783
Date Created
Last Updated 11/09/2009
Status Active
Type
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