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AR# 33800

11.4 PlanAhead - Elaboration fails with std_logic_vector(0:0).


I have a design which contains a std_logic_vector with a width of 1. When I try to elaborate my design within PlanAhead, I get an error similar to the following.

ERROR:Failed to resolve subtree below C:\PlanAhead_Projects\project_1\project_1.srcs\imports\top.v:7: Could not replace (cell 'SRL16REG', library 'work', file 'top.v', netlist 'top') with (cell 'SRL16REG', library 'SRL16REG_lib', file 'SRL16REG.ngc', netlist 'top') because of port interface mismatch; Port 'd' is missing on the replacing cell

This design synthesizes with no problems. How do I run elaboration in PlanAhead?


This is a bug in the elaboration algorithms within PlanAhead and will be fixed in an upcoming release of PlanAhead. If it is necessary to run elaboration in the current PlanAhead release, you'll need to add an HDL wrapper to the netlist with the std_logic_vector(0:0) port.

AR# 33800
Date 12/15/2012
Status Archive
Type General Article
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