MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - Read Modify Write command fails when using Data Mask to mask individual bytes

AR#	33803	Search For Another Answer
Topic	MIG
Last Updated	06/09/2011
Status	Active

Description

The MIG v3.3 Virtex-6 FPGA DDR2/DDR3 designs support Read Modify Write commands. When a Read Modify Write is performed in conjunction with a partial data mask, the modified data is not written to the memory.

Solution

This is a known issue with MIG v3.3 which affects both simulation and hardware. To avoid this issue, Read Modify Write commands should not be performed with a partial data mask. 

This issue is scheduled to be resolved in the next version of MIG (released with ISE Design Suite 12.1).