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AR# 33803

MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - Read Modify Write command fails when using Data Mask to mask individual bytes


The MIG v3.3 Virtex-6 FPGA DDR2/DDR3 designs support Read Modify Write commands.

When a read-modify-write is performed in conjunction with a partial data mask, the modified data is not written to the memory.


This is a known issue with MIG v3.3 which affects both simulation and hardware.

To avoid this issue, read-modify-write commands should not be performed with a partial data mask. 

This issue is scheduled to be resolved in the next version of MIG (released with ISE Design Suite 12.1).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33706 MIG v3.3 - Release Notes and Known Issues for ISE Design Suite 11.4 N/A N/A
AR# 33803
Date Created 11/14/2009
Last Updated 08/20/2014
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • MIG