AR# 33804 MIG v3.3, Virtex-6 FPGA, DDR2 - Timing parameter tRC min is violated if CAS Latency (CL) equals 4 with 2T timing

Description
Solution

The MIG v3.3 Virtex-6 FPGA DDR2 designs violate the tRC timing parameter (Activate to Activate time) for design with CL = 4 using 2T timing.

This issue affects both simulation and hardware. To work around this issue, a CL of 2 can be used.

This issue is resolved in MIG v3.4, whichwas released with ISE Design Suite 12.1.

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AR# 33804
Date Created	11/14/2009
Last Updated	12/15/2012
Status	Active
Type	General Article
Devices	Virtex-6 CXT Virtex-6 HXT Virtex-6 LX More Virtex-6 LXT Virtex-6 SXT Less
IP	MIG

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AR# 33804 MIG v3.3, Virtex-6 FPGA, DDR2 - Timing parameter tRC min is violated if CAS Latency (CL) equals 4 with 2T timing

Description

Solution

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