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MIG v3.3, Virtex-6 FPGA, DDR2 - Timing parameter tRC min is violated if CAS Latency (CL) equals 4 with 2T timing

AR# 33804

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Topic MIG
Last Updated 06/09/2011
Status Active
Description

The MIG v3.3 Virtex-6 FPGA DDR2 designs violate the tRC timing parameter (Activate to Activate time) for design with CL = 4 using 2T timing.

Solution

This issue affects both simulation and hardware. To work around this issue, a CL of 2 can be used.

This issue is resolved in MIG v3.4, which was released with ISE Design Suite 12.1.
Applies To

Devices

  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT

IP

  • MIG
 
 
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