SPI-3 Link Layer v7.1 - Virtex-6 FPGA core timing simulation reports memory collision errors in block RAM

AR#	33809	Search For Another Answer
Topic	IP-Telecom-SPI-3 Link Layer
Last Updated	11/18/2009
Status	Active

Description

Keywords: spi-3. spi3, system, packet, interface, SONET, sonnet, OIF, OC-48, link, layer, POSPHY, POS-PHY

For Virtex-6 FPGA core timing simulations using an SDF file, block RAM memory collision errors occur on the page level. This occurs with cores configured using Independent Clocks and block RAM based FIFOs.

The simulation error message is similar to the following:

"# Memory Collision Error on X_RB36_INTERNAL_VLOG : spi3_link_tb.spi3_link_top0.\spi3_link_rx0/core/core_spi3_link_rx
/core_spi3_link_rx_xst/U0/rx_fifo0/ll_fifo/ll_fifo/grf.rf/mem
/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r
/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram .genblk1.INT_RAMB_TDP.chk_for_col_msg at simulation time 1103.215 ns."

Solution

These collision errors can be ignored as long as the SPI-3 Link Core simulation does not report any data mismatches. The cause of the errors is under investigation.

Revision History
12/02/2009 - Initial Release