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AR# 33817

12.2 EDK, MPMC v6.00.a, Virtex-6 - ERROR:ConstraintSystem:58 - Constraint does not match any design objects

Description

When using MPMC in Virtex-6 FPGA, the following errors occur. How do I resolve these errors/warnings?

ERROR:ConstraintSystem:58 - Constraint <NET */mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/clk_rsync[?]" TNM_NET = TNM_clk_rsync;> [gpx.ucf(46)]: NET "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/clk_rsync[?]" does not match any design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5 ns;> [gpx.ucf(47)]: Unable to find an active 'TNM' or 'TimeGrp' constraint named 'TNM_clk_rsync'.

ERROR:ConstraintSystem:58 - Constraint <INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X1Y141";> [gpx.ucf(209)]:
INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" does not match any design objects.

WARNING:ConstraintSystem:203 - A target design object for the Locate constraint
'<INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X1Y141";> [gpx.ucf(209)]'
could not be found and so the Locate constraint will be removed.

ERROR:ConstraintSystem:58 - Constraint <INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X1Y141";> [gpx.ucf(211)]:
INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" does not match any design objects.

WARNING:ConstraintSystem:203 - A target design object for the Locate constraint
'<INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X1Y141";> [gpx.ucf(211)]'
could not be found and so the Locate constraint will be removed.

ERROR:ConstraintSystem:58 - Constraint <INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X1Y7";> [gpx.ucf(214)]: INST
"*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" does not match any design objects.

WARNING:ConstraintSystem:203 - A target design object for the Locate constraint

'<INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X1Y7";> [gpx.ucf(214)]' could not be found and so the Locate constraint will be removed.

ERROR:ConstraintSystem:58 - Constraint <INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" LOC = "OLOGIC_X2Y141";> [gpx.ucf(218)]:
INST "*/mpmc_0/mpmc_core_0/gen_??_ddr3_phy.mpmc_phy_if_0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" does not match any design objects.

Solution

Additional MPMC parameters must be set in addition to converting the MIG UCF when using the Standalone MIG Flow.

From the MPMC data sheet:

MPMCv6

In Virtex-6 designs, you must:
* Open the generated MIG files and obtain the values needed to set MPMC parameters
C_MEM_NDQS_COL0, C_MEM_NDQS_COL1, C_MEM_DQS_LOC_COL0, and C_MEM_DQS_LOC_COL1.
These parameters are located in the <MIG_project>/user_design/rtl/ip_top directory in the top-level file of your design name. The MIG parameter names do not have the C_MEM_ prefix.
* In the UCF file, use LOC on the MMCM used with MPMC in the same location as specified by MIG.

MPMCv5

In Virtex-6 FPGA designs, you must:
* Open the generated MIG files and obtain the values needed to set MPMC parameters
C_MEM_NDQS_COL0, C_MEM_NDQS_COL1, C_MEM_DQS_LOC_COL0, and C_MEM_DQS_LOC_COL1.
* In the UCF file, use LOC on the MMCMs used with MPMC in the same location as specified by MIG.
The MIG tool specifies two MMCM locations that correspond to the MMCM instance inside MPMC (which has mmcm_clk_base in the name) and the MMCM external to MPMC that drives the MPMC ports MPMC_Clk_Wr_I0, MPMC_Clk_Wr_O0, and MPMC_Clk_Mem. The MMCM location constraints must be transferred to the UCF file of the MPMC design. See "Virtex-6 Clock Logic," page 97, for more information about clocking requirements.

AR# 33817
Date Created 11/12/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • EDK - 11.2
  • EDK - 11.3
  • EDK - 11.4
  • More
  • EDK - 11.5
  • EDK - 12.1
  • EDK - 12.2
  • EDK - 12.3
  • Less
IP
  • Multi-Port Memory Controller (MPMC)