MIG v3.3, Virtex-6 FPGA DDR3 DIMM - MIG does not allocate two sets of CK/CK#, CS and ODT for data widths using two DIMMs

Description

The MIG v3.3 Virtex-6 FPGA DDR3 design should allocate two sets of CK/CK#, CS, and ODT when designs with data widths using two DIMMs are generated (i.e., 144-bit designs using two 72-bit DIMMs). These signals should be replicated for each DIMM, but instead, only one set of these control signals is generated.

Solution