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AR# 33834 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Use of Component Name "core" Causes Implemenation Failures using VHDL Flow

Known Issue: v1.5, v1.4, v1.3

In the CORE Generator customization GUI, if the component name includes "core", it causes XST synthesis to fail.

To work around this issue, do not use "core" in the generated core's component name.

Revision History
04/23/2010 - Updated for ISE 12.1 and v1.5
12/02/2009 - Initial Release

AR# 33834
Date Created 11/16/2009
Last Updated 05/19/2012
Status Active
Type Known Issues
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