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AR# 33835 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Area Group Constraints to Assist in x8 GEN 2 Timing Closure

Description


Known Issue v1.4

These area group constraints are not included in the generated UCF files. They assist in timing closure for x8 GEN 2 designs.

Solution


Add the appropriate constraints to the generated UCF file found in the <core_name>/example_design directory.

For LX75 and LX130:
INST "core/*" AREA_GROUP = "AG_CORE";
AREA_GROUP "AG_CORE" RANGE = SLICE_X56Y0:SLICE_X105Y80;

For LX195 and LX240:
INST "core/*" AREA_GROUP = "AG_CORE";
AREA_GROUP "AG_CORE" RANGE = SLICE_X112Y0:SLICE_X161Y80;

For SX315:
INST "core/*" AREA_GROUP = "AG_CORE";
AREA_GROUP "AG_CORE" RANGE = SLICE_X160Y0:SLICE_X209Y80;

For SX475:
INST "core/*" AREA_GROUP = "AG_CORE";
AREA_GROUP "AG_CORE" RANGE = SLICE_X160Y80:SLICE_X209Y160;

Revision History
12/02/2009 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33763 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5 N/A N/A

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AR# 33835
Date Created 11/16/2009
Last Updated 12/15/2012
Status Active
Type General Article
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  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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