Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Area Group Constraints to Assist in x8 GEN 2 Timing Closure

AR#	33835	Search For Another Answer
Topic	PCIe
Last Updated	08/06/2010
Status	Active

Description

Known Issue v1.4 

 

These area group constraints are not included in the generated UCF files. They assist in timing closure for x8 GEN 2 designs.

Solution

Add the appropriate constraints to the generated UCF file found in the <core_name>/example_design directory. 

 

For LX75 and LX130: 

INST "core/*" AREA_GROUP = "AG_CORE"; 

AREA_GROUP "AG_CORE" RANGE = SLICE_X56Y0:SLICE_X105Y80; 

 

For LX195 and LX240: 

INST "core/*" AREA_GROUP = "AG_CORE"; 

AREA_GROUP "AG_CORE" RANGE = SLICE_X112Y0:SLICE_X161Y80; 

 

For SX315: 

INST "core/*" AREA_GROUP = "AG_CORE"; 

AREA_GROUP "AG_CORE" RANGE = SLICE_X160Y0:SLICE_X209Y80; 

 

For SX475: 

INST "core/*" AREA_GROUP = "AG_CORE"; 

AREA_GROUP "AG_CORE" RANGE = SLICE_X160Y80:SLICE_X209Y160; 

 

Revision History 

12/02/2009 - Initial Release