Boards and Kits Related Issues
(Xilinx Answer 33319) - SP601 - HyperTerminal does not automatically detect USB UART Bridge
(Xilinx Answer 33417) - Spartan-6 FPGA MCB - Spartan-6 FPGA Memory Controller User Guide (UG388) incorrectly states that MIG automatically outputs files for the SP601/SP605 reference boards
(Xilinx Answer 33569) - Development Boards - Where can I find the USB UART driver?
(Xilinx Answer 33610) - SP605 - Preliminary information related to the Spartan-6 FPGA SP605 Evaluation Kit
(Xilinx Answer 34093) - SP605 - Change to resistor network values on the MGT_AVCC rail
(Xilinx Answer 37579) - What device do I have on my board? Is it an Engineering Sample or Production silicon?
(Xilinx Answer 39210) - Boards - Directory structure of CF card changed
(Xilinx Answer 40350) - Development Boards - Do Series 6 Evaluation Kits from Xilinx support eFuse?
(Xilinx Answer 40705) - Development Boards - BRD GUI on Windows 7
(Xilinx Answer 50596) - Xilinx Evaluation Kits - PCIe cards - CE requirements for PC test environment
(Xilinx Answer 53808) - Spartan-6 FPGA SP605 Evaluation Kit - Dimensions changed
Documentation Related Issues
(Xilinx Answer 35087) - SP605 User Guide (UG526) - Discrepancies in Pinouts between User Guide and Schematics
(Xilinx Answer 41050) - UG525 - Typos in Figure 1-1
(Xilinx Answer 42252) - UG526 - UART and USB ports labeled incorrectly in Figure 1-2
(Xilinx Answer 46428) - XTP065 SP605 PCIe x1 Gen1 Design Creation - S1 should be set to '0000'
PCI Express Related Issues
(Xilinx Answer 33665) - 11.3 CORE Generator - Why am I unable to select the -3 speed grade for the PCIe core generation for the Spartan-6 FPGA xc6slx45t part that is on the SP605 board?
(Xilinx Answer 34404) - SP605 Schematics - PCI Express Endpoint Connectivity section shows clock net name PCIE_250M_N. Should this really be PCIE_125M_N?
Design Tools Related Issues
(Xilinx Answer 34203) - 11.x ChipScope - IBERT - Spartan-6, Virtex-5, Virtex-6 - PCS loopback results in an increasing error count
(Xilinx Answer 52472) - 14.x - 6 Series Boards and Kits - Are TRDs and Example Designs available for 14.x?
11.5 DesignTools Information
11.5 includes important updates and supports production devices for the Virtex-6 and Spartan-6 device families. However, several work-arounds might be required for Virtex-6 and some Spartan-6 FPGA customers using ISE 11.5 design tools. Please review (Xilinx Answer 32147) before you upgrade to 11.5. These work-arounds are addressed in ISE 12.1 design tools, released in May 2010.
12.1 Design Tools Information
At this time, SP605 Evaluation Kits are not shipped with the 12.1 version of ISE Design Suite. The reference designs (shipped with the kits and available on-line) are only supported in version 11.4 of the tools.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 43750 | Xilinx Boards and Kits Solution Center - Top Issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46428 | SP605 PCIe x1 Gen1 Design Creation (XTP065) - S1 should be set to '0000' | N/A | N/A |
| 42252 | UG526 - UART and USB ports labeled incorrectly in Figure 1-2 | N/A | N/A |
| 41050 | UG525 - Typos in Figure 1-1 | N/A | N/A |
| 35087 | SP605 User Guide (UG526) - Discrepancies in Pinouts between User Guide and Schematics | N/A | N/A |
| 34203 | 11.x ChipScope - IBERT - Spartan-6, Virtex-5, Virtex-6 - PCS loopback results in an increasing error count | N/A | N/A |
| 34093 | SP605 - Change to resistor network values on the MGT_AVcc rail | N/A | N/A |
| 40705 | Development Boards - BRD GUI on Windows 7 | N/A | N/A |
| 39210 | Boards - Directory structure of CF card changed | N/A | N/A |
| 50596 | Xilinx Evaluation Kits - PCIe Cards - CE Requirements for PC Test Environment | N/A | N/A |
| 53808 | Spartan-6 FPGA SP605 Evaluation Kit - Dimensions changed | N/A | N/A |
| 54749 | Board Temperature Specifications for 6 Series Kits | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46428 | SP605 PCIe x1 Gen1 Design Creation (XTP065) - S1 should be set to '0000' | N/A | N/A |
| 34404 | SP605 Schematics - PCI Express Endpoint Connectivity section shows clock net name PCIE_250M_N. Should this really be PCIE_125M_N? | N/A | N/A |
| 34093 | SP605 - Change to resistor network values on the MGT_AVcc rail | N/A | N/A |
| 37579 | Which device do I have on my Xilinx Evaluation Kit? Is it an Engineering Sample (ES) or Production silicon? | N/A | N/A |