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Block Memory Generator v3.3 - Asynchronous Reset does not function correctly in Automotive Spartan-6 FPGA behavioral model

AR# 33842

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Topic IP-SysLogic-BlockMem Generator
Last Updated 11/18/2009
Status Active
Description

Keywords: sim, simulation, async, core

Using the Block Memory Generator v3.3, the asynchronous reset does not function correctly in my VHDL behavioral model when the Reset Priority is set to CE (Latch or Register Enable). Why?

Solution

This is a known issue which only affects the VHDL behavioral model.

To work around this issue, use the structural model or the verilog behavioral model.
 
 
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