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AR# 33842

Block Memory Generator v3.3 - Asynchronous Reset does not function correctly in Automotive Spartan-6 FPGA behavioral model


Using the Block Memory Generator v3.3, the asynchronous reset does not function correctly in my VHDL behavioral model when the Reset Priority is set to CE (Latch or Register Enable). Why?


This is a known issue which only affects the VHDL behavioral model.  


To work around this issue, use the structural model or the verilog behavioral model.

AR# 33842
Date Created 11/18/2009
Last Updated 05/23/2014
Status Archive
Type General Article