Known Issues: v1.13, v1.12
In the top level file which has the same name of the generated core found in the <core name>/source directory, there are the following connections on the instance for pcie_ep_top:
.gt_txbuffctrl_0 ( TXBUFFCTRL),
.gt_txbuffctrl_1 ( TXBUFFCTRL),
The problem is that TXBUFFCTRL is not being defined in this file. This causes XST to tie the TXBUFFCTRL signal to ground resulting in the MGT port TXBUFFDIFFCTRL to be tied to 000 instead of the default 100.