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AR# 33849

Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values

Description

The Virtex-6 FPGA MMCM has the following new requirements:
  1. A calibration circuit is required to be inserted into the user design for all MMCM designs.
  2. The minimum VCO frequency of the MMCM is now 600 MHz.
  3. The CLKFBOUT_MULT_F attribute (the multiply of the MMCM) cannot be set to fractional values, or a value of 1, 2, 3, or 4.

The requirements will be checked by the software starting in the 11.5 ISE Design Suite update (now available).

More details on each of these requirements are described below.

Solution

1. Calibration Circuit Requirement

Any design using the MMCM requires a calibration circuit to be inserted in the design and simulation models to be updated. With the addition of the calibration circuit, the STARTUP_WAIT attribute is no longer supported for the MMCM.

11.5 ISE and later software tools automatically insert the circuit into designs using MMCMs during the MAP phase of software implementation.

11.4 ISE and previous software tools require the circuit to be manually inserted into designs using MMCMs. To obtain the necessary files, please contact Xilinx Technical Support.

When upgrading to 11.5 ISE, users who have designs with the manually inserted circuit can either remove the circuit or disable the insertion of the circuit by placing the INSERT_MMCM_PHASE_CALIBRATION=FALSE attribute on each applicable MMCM.Apply the attribute in the UCF file with the following syntax:

INST your_mmcm_adv_inst INSERT_MMCM_PHASE_CALIBRATION="FALSE";

2. Minimum VCO Frequency = 600 MHz

The new requirement for minimum VCO frequency affects any users having an MMCM VCO frequency under 600 MHz. Affected customers are users of IP (listed below), Clocking Wizard users, and those who have directly instantiated the MMCM in a design. The following information is to help you understand if you are affected and how to obtain the work-around.

IP Users:

Check the following list and implement the work-around listed in the linked Answer Record. Any IP not listed are not affected by the new minimum VCO frequency.


Clocking Wizard Users:
Check the VCO frequency used by the core and adjust DIVCLK_DIVIDE and CLKFBOUT_MULT_F attributes until the VCO is in the valid range. Use the override section on page 4 of the core to adjust the values. More information on these attributes can be found in the Virtex-6 Clocking ResourcesUser Guide (UG362): http://www.xilinx.com/support/documentation/user_guides/ug362.pdf


3. CLKFBOUT_MULT_F cannot be set to1-4 or fractional values


The new requirement for the CLKFBOUT_MULT_F attribute affects any users having an MMCM multiply value (CLKFBOUT_MULT_F) that is set to2, 3,4, or a fractional value.Affected customers are certain IP users (listed below), Clocking Wizard users, and those who havedirectly instantiatedthe MMCM in a design. The following information is to help you understand if you are affected and to obtain work-around information. Note that CLKFBOUT_MULT_F=1 is not allowed because of Fpfdmax and Fvcomin restrictions, and this is not a new requirement.

IP Users:

Check the following list and implement the work-around in the linked answer record. Any IP not listed are not affected by the new CLKFBOUT_MULT_F = 4 or fractional value restriction. The list is still being updated to reflect any IP that are affected by the CLKFBOUT_MULT_F=2 and 3 restriction.

Clocking Wizard Users:

Check theCLKFBOUT_MULT_F valueused by the core and adjust DIVCLK_DIVIDE and CLKFBOUT_MULT_F attributes. Use the override section on page 4 of the core to adjust the values. More information on these attributes can be found in the Virtex-6 Clocking Resources User Guide (UG362):http://www.xilinx.com/support/documentation/user_guides/ug362.pdf

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A
32929 Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA N/A N/A

Child Answer Records

Associated Answer Records

AR# 33849
Date Created 11/19/2009
Last Updated 06/20/2012
Status Active
Type Design Advisory
Devices
  • Virtex-6 SXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 CXT
Tools
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5