UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33850

Endpoint Block Plus Wrapper v1.13 for PCI Express - Reading and Writing Configuration Space Registers Fails

Description

Reading or writing to the configuration space registers using the user application configuration port might fail if the read is performed too close to trn_lnk_up_n assertion, or the write is performed too close to the trn_reset_n deassertion.

Solution


Configuration space reads using the user application configuration port should not be performed until 20 clock cycles after trn_lnk_up_n assertion. The read enable signal, cfg_rd_en_n, should until cfg_rd_wr_done asserts. If cfg_rd_wr_done is not asserted within 15 clock cycles, then the read failed to complete and it should be tried again. Reads might sometimes fail to complete depending on if the Block Plus wrapper is accessing the block's management port.
Writes to the configuration space must not be issued until at least 10 clock cycles after the deassertion of trn_reset_n. Writes can only be performed in the period between trn_reset_n deassertion and trn_lnk_up_n assertion. For more information on this topic, see the Block Plus User Guide (UG341).
The Block Plus User Guide (UG341) for v1.14 (to be released in 12.1) is to contain these restrictions regarding how long to wait until reads and writes can be performed.
Revision History
06/15/2010 - Updated requirements of holding cfg_rd_en_n asserted
01/19/2010 - Initial Release
AR# 33850
Date Created 01/20/2010
Last Updated 05/22/2012
Status Active
Type Known Issues
IP
  • Endpoint Block Plus Wrapper for PCI Express