We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33873

11.3 Virtex-5 FPGA PLACE - ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region CLOCKREGION_X0Y0


My design appears to run through MAP successfully, but then fails in the end with this DRC issue. Is this a problem with my design or a tool issue?

ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region CLOCKREGION_X0Y0. The IODELAY block
DDR2_SDRAM_16Mx32/DDR2_SDRAM_16Mx32/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce has an IDELAY_TYPE attribute of either FIXED or VARIABLE. This programming requires that there be an
IDELAYCTRL block programmed within the same clock region.


IDELAYCTRL and IODELAY components require some special handling because of the way they are modeled by the software. There is no connectivity between the IDELAYCTRL and IODELAY components to indicate to the placer algorithms which components are associated with each other. For this reason, the designer must use constraints to create an association in one of the following ways:

1. An IODELAY_GROUP can be defined to group a single IDELAYCTRL with one or more IODELAYs. Each group must have at least one of each component and no more than one IDELAYCTRL. If the group is placed across more than one clock region, the IDELAYCTRL will be replicated. This is the new and suggested methodology in the 11.x tools.

2. An IDELAYCTRL can be LOC'd to a clock region and will be grouped with IODELAYs placed in that region usually due because of constraints on the associated IOBs.

3. Any unconstrained and ungrouped IDELAYCTRL/IODELAY logic will become a default group and be treated according to the rules in (1). For that reason, no more than one IDELAYCTRL can be unconstrained.

If the IODELAY_GROUPSs are properly defined in a design, but the DRC error is still encountered, there could then be a problem with the IDELAYCTRL replication algorithm not working properly. In that case, a webcase can be opened and the design investigated for a replication issue.
AR# 33873
Date Created 11/24/2009
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
  • ISE Design Suite - 11.3