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AR# 33877

11.4 System Generator for DSP - "ERROR:HDLCompiler:377 - Entity port sl_addrack does not match with type std_logic of component port sl_addrack is declared here"

Description

Why do I receive the following error when I synthesize my Spartan-6 or Virtex-6 FPGA design with a System Generator PCORE in EDK?

"ERROR:HDLCompiler:377 - Entity port sl_addrack does not match with type std_logic of component port sl_addrack is declared here"

Solution

This error is due to a change in the HDL parser for Spartan-6 and Virtex-6 devices, see (Xilinx Answer 32981) for details. This issue is scheduled to be fixed in the next release of System Generator for DSP.

To work around the problem, update the file <sysgen_install>\data\pcoreiface\Xilinx\plb\bus_info.

Open the file in a text editor, delete the existing code and paste the following text into it:

{

'params' => {

'C_SPLB_AWIDTH' => {

'value' => 32,

'type' => 'INTEGER',

'range' => '32 to 36',

'assignment' => 'CONSTANT',

},

'C_SPLB_DWIDTH' => {

'value' => 32,

'type' => 'INTEGER',

'range' => '32 to 128',

},

'C_SPLB_MID_WIDTH' => {

'value' => 1,

'type' => 'INTEGER',

'range' => '0 to 4',

},

'C_SPLB_NUM_MASTERS' => {

'value' => 1,

'type' => 'INTEGER',

'range' => '1 to 16',

},

'C_SPLB_SUPPORT_BURSTS' => {

'value' => 0,

'type' => 'INTEGER',

'assignment' => 'CONSTANT',

},

'C_SPLB_NATIVE_DWIDTH' => {

'value' => 32,

'type' => 'INTEGER',

'assignment' => 'CONSTANT',

'range' => '32 to 32',

},

},

'name' => 'SPLB',

'type' => 'PLBV46',

'std' => 'SLAVE',

'clks' => {

'SPLB_Clk' => 0,

},

'resets' => {

'SPLB_Rst' => 0,

},

'inports' => {

'PLB_ABus' => 32,

'PLB_PAValid' => 0,

'PLB_RNW' => 0,

'PLB_wrDBus' => 32,

},

'outports' => {

'Sl_addrAck' => 0,

'Sl_rdComp' => 0,

'Sl_rdDAck' => 0,

'Sl_rdDBus' => 32,

'Sl_wait' => 0,

'Sl_wrDAck' => 0,

'Sl_wrComp' => 0,

},

}

AR# 33877
Date Created 11/25/2009
Last Updated 12/15/2012
Status Active
Type General Article