LogiCORE IP Display Port v1.1 - Why does my VHDL Instantiation template fail when I attempt to simulate or synthesize the transmitter source design?

AR#	33885	Search For Another Answer
Topic	IP-DSP MVI
Last Updated	12/02/2009
Status	Active

Description

Keywords: display port, vhdl, ports, template, vho

Why does my VHDL Instantiation template fail when I attempt to simulate or synthesize the transmitter source design?

Solution

This is because there is an extra "." in the <core name>.vho port list that needs to be removed.

You can fix this by removing the "." from in front of all the ports.
There is a sample of some of the ports.
From:

your_instance_name : core
port map (
.reset => reset,
.apb_clk => apb_clk,
.apb_select => apb_select,
.apb_enable => apb_enable,
.apb_write => apb_write,
.apb_addr => apb_addr,
.apb_wdata => apb_wdata,
.apb_int => apb_int,
.apb_rdata => apb_rdata,
...



To:

your_instance_name : core
port map (
reset => reset,
apb_clk => apb_clk,
apb_select => apb_select,
apb_enable => apb_enable,
apb_write => apb_write,
apb_addr => apb_addr,
apb_wdata => apb_wdata,
apb_int => apb_int,
apb_rdata => apb_rdata,
...




Please see (Xilinx Answer 33258) for a detailed list of LogiCORE Display Port Release Notes and Known Issues.